Semiconductor assembly without adhesive fillets

ABSTRACT

Disclosed is a method for forming a semiconductor assembly and the resulting assembly in which a flowable adhesive material which secures a die to a support and does not form an adhesive fillet. A flowable adhesive is deposited between the die and support so that it covers about 50 to about 90 percent of the bottom surface area of the die after the die is mounted to the support. The reduced surface coverage area prevents formation of an adhesive fillet.

FIELD OF THE INVENTION

[0001] The present invention relates to a structure and method offorming a semiconductor assembly using adhesive materials to securesemiconductor dies to support elements without forming adhesive fillets.

BACKGROUND OF THE INVENTION

[0002] In order to reduce the size of semiconductor devices numeroustechniques have been developed to vertically stack one semiconductordie, hereinafter “die”, on top of another die. FIG. 1 illustrates aconventional method of vertically stacking two die 20, 30 on a supportstructure 10, such as a printed circuit board (PCB) or other thinsupport structure, to form a conventional semiconductor assembly 100.The first die 20 is shown secured to a support structure 10 by anadhesive material 22 using techniques well known in the art. When thefirst die 20 is pressed against the support structure 10 the adhesivematerial 22 is partially forced outside the die's perimeter 29 and formsan adhesive fillet 24. Likewise, when the second die 30 is securedagainst the first die 20 by an adhesive material 22 a second adhesivefillet 24 is also formed.

[0003] Both the first die 20 and second die 30 are shown wire bonded 40to an electrical contact area 18 on the support structure 10. The firstdie 20 has an electrical contact area 28, such as a bonding pad, on itstop surface 26. Because adhesive fillet 24 is formed when the second die30 is secured to the first die 20, it limits the placement of the firstdie's 20 electrical contact area 28. The distance B between theperimeter 39 of the second die 30 and the first die's electrical contactarea 28 must be increased by distance A, the width of the adhesivefillet 24, to provide sufficient operating space for the wire bondingequipment. Typical dimensions for distances B are about 428 microns orgreater to allow for adhesive fillets 24, which are conventionally about228 microns in width or greater. Using current wire bonding equipment,distance B between electrical contact area 28 and the perimeter of thefillet 24 can be reduced to about 200 microns or less. In other words,adhesive fillet 24 requires about 228 microns or more of first die's topsurface 26 on each side of the first die 20. If the adhesive fillet 24were eliminated the space could be used either to increase the size ofthe second die 30 or to reduce the size of the first die 20.

[0004] An alternative method of stacking dies 20, 30 to a supportstructure 10 to form a semiconductor assembly involves using an adhesivefilm sized and aligned with the respective die 20, 30 perimeters. Sincethe adhesive film is cut or dimensioned with the second die's perimeter39, no adhesive fillet 24, as described above, is formed. However,adhesive films are expensive and are difficult to align with the dies20, 30 and support structure 10. Accordingly, there is a need and desirefor an easy, low-cost method of securing one or more semiconductor dies20, 30 to various support structures 10 to form a semiconductor assembly100 using adhesive materials 22 such that no adhesive fillets 24 areproduced, for example, when a second die 30 is pressed and secured to afirst semiconductor die 20 and when a first semiconductor die 20 ispressed and secured to a support structure 10.

SUMMARY OF THE INVENTION

[0005] The present invention provides a method to vertically stack atleast one semiconductor die on top of another semiconductor die using anadhesive material without forming an adhesive fillet at the second die'sperimeter. An adhesive material is deposited over about 50% to about 90%of the top surface of the first semiconductor die, such that when thesecond die is secured against the adhesive material and first die noadhesive material extends past the perimeter of the second die. Becauseno adhesive fillet is formed, the distance between the electricalcontact areas on top of the first semiconductor die and the perimeter ofthe second die can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of the preferredembodiments given below with reference to the accompanying drawings inwhich:

[0007]FIG. 1 is an illustration of a conventional structure in which twostacked semiconductor die are secured to a support structure by anadhesive material;

[0008]FIG. 2 is a plan view of a partially fabricated semiconductor diestack on a support structure according to the present invention;

[0009]FIG. 3 is an elevation view of FIG. 2;

[0010]FIG. 4 is a plan view of a partially fabricated semiconductor diestack at a stage of processing subsequent to that shown in FIGS. 2 and3;

[0011]FIG. 5 is an elevation view of FIG. 4;

[0012]FIG. 6 is a cross-sectional illustration of an encapsulatedsemiconductor die stack formed according to a method of the presentinvention; and

[0013]FIG. 7 is an exemplary embodiment of two semiconductor diesstacked on top of a semiconductor die according to a method of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The invention provides a method and resulting structure for asemiconductor assembly with no adhesive fillet formed when asemiconductor die is secured by adhesive to a supporting structure. Theinvention will be described as set forth in the exemplary embodiments ofthe detailed description and as illustrated in FIGS. 2-7. Theseembodiments are described with sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be employed, and that structural changes may bemade without departing from the spirit or scope of the invention. Theinvention is not limited by the description of the exemplaryembodiments.

[0015] Referring now to the drawings, where like elements are designatedby like reference numerals, FIGS. 2-3, illustrate a plan and elevationview respectively of a partially completed semiconductor assembly 200 inwhich a first semiconductor die 20 is secured to the top surface 16 ofsupporting structure 10, by a first adhesive layer 22. Supportingstructure 10 in an exemplary embodiment is a printed circuit board orthin film, but may be any structure suitable for supporting asemiconductor die. The supporting structure 10 is shown as having twoelectrical contact areas 17 on surface 16 and the first die 20 is alsoshown as having two electrical contact areas 28. It is to be understoodthat any number of electrical contact areas 17, 28 may be provided onthe support structure 10 and first die 20. Also, although FIG. 2 showsthe contact areas 17, 28 as recessed, they may also be formed on thesurface of the support structure 10 or first die 20, respectively, andcould be electrically connected to external electrical paths or to otherparts of the completed semiconductor assembly 200.

[0016] A second adhesive layer 22 is shown in FIG. 2 as deposited on thetop surface 26 of the first semiconductor die 20 within an adhesivelayer area defined by a perimeter 34. The second adhesive layer 22 canbe deposited by techniques well-known in the art to include variouspatterns and coverage areas. It is to be understood that perimeter 34 isrepresentative of an area of deposition of the second adhesive layer 22;however it is not limiting. In accordance with the invention asufficient amount of adhesive material 22 should be deposited toadequately secure the second semiconductor die 30 (see FIGS. 4-5) to thefirst semiconductor die 20. The invention includes any coverage area orpattern that does not exceed the perimeter of the second die 30. Asdescribed below, when the second die 30 is placed and pressed on thefirst die 20, the adhesive layer 22 represented inside of the adhesiveperimeter 34 does not extend past the profile or perimeter 39 of thesecond die 30 (FIGS. 4-5).

[0017] FIGS. 4-5 show the assembly 200 after a second die 30 withelectrical contact areas 38 on the die's top surface 36 is pressedagainst the second adhesive layer 22 located on the top surface 26 ofthe first die 20. A cavity 24 is formed between the dies 20 and 30 andis characterized by a distance D between the perimeter 34 of the secondadhesive layer 22 and the perimeter 39 of the second die 30. Thedistance D may be a regular or irregular distance around the peripheryof the adhesive layer 22. It is to be understood that formation ofcavity 24 is not essential, what is important is that adhesive layer 22does not extend beyond the perimeter 39 of the second die 30 such thatno adhesive fillet 24 is formed.

[0018] If cavity 24 is present, the distance D is preferably in therange such that between about 50 and about 90 percent of the second die30 bottom surface is covered by the second adhesive material layer 22.FIGS. 4 and 5 show distance C between the perimeter 39 of the second die30 and the perimeter 29 of the first die 20. This distance is a valuewhich provides acceptable clearance between electrical contact area 28and the second die 30 to enable the formation of electrical contactsbetween the dies 20, 30 and other parts of the assembly 20 such as wirebonds 40 between the dies 20, 30 and the support structure 10 (FIGS. 6).An exemplary distance C between the perimeters 29, 39 of the first die20 and second die 30 is about 200 microns or less. The distance C iscurrently only limited by the technology of the wire bond equipment andthe minimum required operating space.

[0019]FIG. 6 is a cross-sectional illustration of the semiconductorassembly 200 after electrical connections 40 have been made between therespective electrical contact areas 28 and 38 of the first die 20 andsecond die 30 and electrical contact areas 17 of the support structure10. In an exemplary embodiment, wire bonding is used for theseconnections. As illustrated, the dies 20, 30 are stacked and positionedin such a manner that at least one of the electrical contact areas 28,38 for each die 20, 30 is exposed and accessible for making theelectrical connection. Illustrated distance E represents the distancebetween the first die's electrical contact area 28 and the perimeter 39of the second die 30.

[0020] Also shown are the balls 60 which make up a ball grid arraypattern for making electrical connections between the support structure10 and external electrical circuits. The balls 60 are deposited on thesupport structure 10 using materials and techniques well known in theart and are electrically connected through conductors supported bysupport structure 10 to the contact areas 17. It is to be understoodthat multiple semiconductor assemblies 200 could be prepared at one timeon a continuous support structure 10, which could be separated intoindividual or multiple semiconductor assemblies 200 at a later stage offabrication.

[0021]FIG. 6 also shows an encapsulating material 50, such as a moldingcompound, deposited over the wire bonds 40, semiconductor dies 20, 30,and top surface 16 of the support structure 10. As an exemplaryillustration, some of the encapsulation material 50 is shown under thesecond die 30 and within cavity 24 (FIGS. 4-5) and provides support andstability to the second die 30. The encapsulating material 50 andmolding techniques using it are well known in the art and not repeatedherein.

[0022]FIG. 7 is a cross-sectional illustration of a second exemplaryembodiment of a semiconductor assembly 300 with second and thirdsemiconductor dies 30, 40 secured to a first semiconductor die 20 usingthe techniques described above. It is to be understood that theelimination of the adhesive fillet 24 as discussed in FIG. 1 covers awide range of semiconductor configurations involving multiple dies withvarious sizes, dimensions, and electrical contact techniques. The abovedescribed invention has the advantage of allowing either the size of thesecond and third semiconductor dies 30, 40 to be increased or allowingthe size of the first semiconductor die 20 to be reduced by eliminatingthe wasted space occupied by the adhesive fillet 24.

[0023] Having thus described in detail the exemplary embodiments of theinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description as many apparent variations thereof are possiblewithout departing from the spirit or scope of the invention.Accordingly, the above description and accompanying drawings are onlyillustrative of exemplary embodiments which can achieve the features andadvantages of the present invention. It is not intended that theinvention be limited to the embodiments shown and described in detailherein. The invention is only limited by the scope of the followingclaims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A semiconductor assembly comprising: a supportstructure having a top surface; and at least one semiconductor diehaving a top and bottom surface, said bottom surface having a smallerarea than said top surface of said support structure, said at least onesemiconductor die being secured at its bottom surface to said topsurface of said support structure by a flowable adhesive material whichdoes not extend past the perimeter of said at least one semiconductordie.
 2. The semiconductor assembly of claim 1, wherein said supportstructure is a film.
 3. The semiconductor assembly of claim 1, whereinsaid support structure is a printed circuit board.
 4. The semiconductorassembly of claim 1, wherein said support structure is at least onesemiconductor die with a top and bottom surface.
 5. The semiconductorassembly of claim 1, wherein said flowable adhesive material is anepoxy.
 6. The semiconductor assembly of claim 1, wherein said flowableadhesive material covers an area less than or equal to about 90% of saidat least one semiconductor die bottom surface area.
 7. The semiconductorassembly of claim 6, wherein said flowable adhesive material covers anarea greater than or equal to about 50% of said at least onesemiconductor die bottom surface area.
 8. The semiconductor assembly ofclaim 1, wherein said top surface of said support structure has at leastone electrical contact area and a distance between an electrical contactarea and said perimeter of said at least one semiconductor die is lessthan or equal to about 428 microns.
 9. The semiconductor assembly ofclaim 8, wherein a distance between an electrical contact area and saidperimeter of said at least one semiconductor die is less than or equalto about 200 microns.
 10. The semiconductor assembly of claim 1, whereinsaid at least one semiconductor die is in electrical communication withat least one electrical contact area provided on said support structure.11. The semiconductor assembly of claim 10, wherein said electricalcommunication is through a wire bond.
 12. The semiconductor assembly ofclaim 10, wherein said at least one electrical contact area is a bondingpad.
 13. The semiconductor assembly of claim 10, further comprising anencapsulating material for encapsulating said die, electricalcommunication, and at least a portion of said support structure.
 14. Thesemiconductor assembly of claim 13, wherein said encapsulating materialfills in at least some portion of a space between said bottom surface ofsaid die and said top surface of said support structure.
 15. Asemiconductor assembly comprising: a first semiconductor die having atop and a bottom surface; and a second semiconductor die having a topand bottom surface, said bottom surface having a smaller area than saidtop surface of said first semiconductor die, said second die beingsecured at its bottom surface to said top surface of said firstsemiconductor die by a flowable adhesive material which does not extendpast the perimeter of said second semiconductor die.
 16. Thesemiconductor assembly of claim 15, wherein said first semiconductor dieis secured to a support structure.
 17. The semiconductor assembly ofclaim 16, wherein said support structure is a film.
 18. Thesemiconductor assembly of claim 16, wherein said support structure is aprinted circuit board.
 19. The semiconductor assembly of claim 15,wherein said flowable adhesive material is epoxy.
 20. The semiconductorassembly of claim 15, wherein said flowable adhesive material covers anarea less than or equal to about 90% of said second semiconductor die'sbottom surface area.
 21. The semiconductor assembly of claim 20, whereinsaid flowable adhesive material covers an area greater than or equal toabout 50% of said second semiconductor die's bottom surface area.
 22. Asemiconductor assembly comprising: a first semiconductor die having atop and a bottom surface; a second semiconductor die having a top and abottom surface, said bottom surface having a smaller area than said topsurface of said first semiconductor die; a third semiconductor diehaving a top and a bottom, said bottom surface having a smaller areathan said top surface of said first semiconductor die, said second andthird semiconductor dies being secured at their bottom surface to saidtop surface of said first semiconductor die by a flowable adhesivematerial which does not extend past the perimeter of said secondsemiconductor die or said third semiconductor die.
 23. The semiconductorassembly of claim 22, wherein said bottom surface of said firstsemiconductor die is secured to a support structure.
 24. Thesemiconductor assembly of claim 22, wherein said flowable adhesivematerial is epoxy.
 25. The semiconductor assembly of claim 24, whereinsaid flowable adhesive material covers an area less than or equal toabout 90% of said second semiconductor die's bottom surface area andsaid third semiconductor die's bottom surface area.
 26. Thesemiconductor assembly of claim 22, wherein said flowable adhesivematerial covers an area greater than or equal to about 50% of saidsecond and said third semiconductor die's bottom surface area.
 27. Asemiconductor assembly comprising: a support structure; a firstsemiconductor die having a top and bottom surface, said bottom surfacebeing secured to said support structure; and a second semiconductor diehaving a top and bottom surface, said bottom surface having a smallerarea than said top surface of said first semiconductor die,, said seconddie being secured at its bottom surface to said top surface of saidfirst semiconductor die by a flowable adhesive material which does notextend past the perimeter of said second die.
 28. The semiconductorassembly of claim 27, wherein said top surface of said firstsemiconductor die has at least one electrical contact area and adistance between an electrical contact area and said perimeter of saidsecond semiconductor die is less than or equal to about 428 microns. 29.The semiconductor assembly of claim 28, wherein a distance between anelectrical contact area on said top surface of said first semiconductordie and said perimeter of said second semiconductor die is less than orequal to about 200 microns.
 30. The semiconductor assembly of claim 27,wherein at least one of said first and said second semiconductor diesare in electrical communication with said support structure.
 31. Thesemiconductor assembly of claim 27, wherein said second semiconductordie is in electrical communication with an electrical contact area onsaid first semiconductor die.
 32. A method of manufacturing asemiconductor assembly comprising: depositing a flowable adhesivematerial on a bottom surface of a semiconductor die; providing asupporting structure for said at least one semiconductor die, whereinsaid supporting structure has a perimeter greater than a perimeter ofsaid at least one semiconductor die and has at least one electricalcontact area located adjacent an edge of said semiconductor die; andapplying a force between said at least one semiconductor die and saidsupporting structure causing said flowable adhesive to flow but notextend past the perimeter of said at least one semiconductor die. 33.The semiconductor assembly of claim 32, wherein, said flowable adhesivematerial covers an area greater than or equal to about 50% and less thanor equal to about 90% of said bottom surface of said at least onesemiconductor die.
 34. A method of forming a semiconductor assemblycomprising the steps of: providing a first semiconductor di e having atop and bottom surface and at least one electrical contact area adjacentan edge of said top surface; providing a second semiconductor die havinga top and bottom surface; depositing a flowable adhesive material onsaid top surface of said first die so that said flowable adhesivematerial covers an area no less than or equal to about 50% and nogreater than or equal to about 90% of said second die bottom surfacearea; pressing said second die against said first die so that saidflowable adhesive material flows but does not extend past the perimeterof said second die.
 35. The method of claim 34, further comprising thesteps of securing said bottom surface of said first die to a supportstructure.
 36. The method of claim 35, where said support structure is aprinted circuit board.
 37. The method of claim 35, where said supportstructure is a film.
 38. The method of claim 34, wherein said flowableadhesive material is an epoxy.
 39. A method of forming a semiconductorassembly comprising the steps of: providing a first semiconductor diehaving a top and bottom surface and at least one electrical contact areaadjacent an edge of said top surface; providing a second semiconductordie having a top and bottom surface; depositing a flowable adhesivematerial on said bottom surface of said second die so that said flowableadhesive material covers an area greater than or equal to about 50% andless than or equal to about 90% of said second die bottom surface area;pressing said second die against said first die so that said flowableadhesive material flows out but does not extend past the perimeter ofsaid second die.